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PCIe Gen 4.0 Layout Guidelines: Practical Design Rules

· 5 min read
Radu S
Radu S
Second of his name. Rattler of bits and bobs.

PCB layout is increasingly critical in modern engineering due to the trend toward faster, more integrated, and smaller form factors. While this specific guide focuses on PCIe Gen 4.0 devices and interfaces, the core principles of impedance control, return path management, and noise isolation apply universally across all the multidisciplinary systems built on high-speed transmission lines.

With disciplined layout practices, EMI problems like reflection or crosstalk can be minimized to meet strict high-speed specifications across any of these domains.

1. PCIe Specific Standard Parameters​

Differences in high-speed standards must be accounted for when designing system layouts. Crucial parameters include data rates, inter/intra-pair skew, and trace impedance.

Table: Key Parameters of the PCIe Standard

ParameterValue
Frequency / Data RateGen 3: 4 GHz (8 Gbps)
Gen 4: 8 GHz (16 Gbps)
AC Coupling Capacitors75 nF – 220 nF
Polarity ReversalAllowed
Max Intra-Pair Skew5 mils
Max Inter-Pair SkewNo Inter-pair specification
Trace Impedance (Gen 3 & 4)85 Ω ±5% differential; 42.5 Ω ±5% single-ended

2. High-Speed Signal Layout Guidelines​

  1. Impedance Matching: It is said that PCIe can run on wet string, due to the robust encoding, however, a designer would design trace impedance to minimize reflections. Strictly control the differential trace impedance as close to 85 Ω as possible.
  2. Minimize Length: Keep the total trace length for signal pairs to an absolute minimum, particularly in tight enclosures.
  3. Length Matching: Match the etch lengths of the relevant differential pair traces. Intra-pair skew must be within 5 mils for the PCIe standard.

Image of differential pair intra-pair skew and inter-pair skew

  1. Crosstalk Mitigation: To minimize crosstalk in high-speed interface implementations, the spacing between different signal pairs must be a minimum of 5 times the width of one trace (the 5W rule).
  2. Layer Selection: Route high-speed differential pair signals on the top or bottom layer of the PCB with an adjacent unbroken GND layer. Stripline routing (inner layers) of high-speed differential signals is generally not recommended unless strictly necessary for density, and requires careful return path management.
  3. Bend Geometry: Avoid right-angle bends. Route them with at least two 45° corners. To minimize any impedance change, the official guidelines propose smooth, rounded bends, however, as far as literature goes, there have been no credible research papers that can justify that rounded bends or 45° corners have any signifficant difference in trace impedance.

Image of poor and good right angle bends on a PCB trace

3. Vias, Stub, and ESD/EMI Layout Guidelines​

The use of vias is essential in dense routings, but vias add parasitic inductance and capacitance. Reflections occur due to the change in characteristic impedance, and they effectively increase the trace length. Avoid routing high-speed traces through vias whenever possible.

If it is impossible to avoid vias:

  • Via Count: Ensure the via count on each member of the differential pair is equal and symmetrical. A maximum of two vias is recommended for high-speed traces over 5 Gbps.
  • Return Current: Be extremely careful with the return current when changing layers. Place ground vias immediately adjacent to the signal vias to ensure the return current flows as close as possible to the signal.

Image of differential pair via return path with adjacent GND vias

  • Via Stubs: Longer via stubs resonate at lower frequencies and heavily increase insertion loss. Keep stubs as short as possible (less than 15 mils). For thick boards, longer stubs should be back-drilled.

Image of long PCB vias with back-drilled stubs

  • Component Voids: When incorporating ESD/EMI components, or AC coupling capacitors, incorporate voids in the reference plane directly under the component signal pads to reduce parasitic capacitance and losses.

  • Component Selection: Use 0402 0-Ω resistors for common-mode filter (CMF) no-stuff options. Keep the overall routing of AC coupling capacitors and ESD protection as short and as close to the connector as possible. Do not place test points on high-speed differential signals.

4. Power and Grounding Layout Guidelines​

  1. Plane Integrity: Use a complete, unbroken ground plane and a complete power plane to avoid noise coupling. If split ground planes are absolutely essential:
    • Never route signals over a gap in the reference plane. Always ensure the return current flow has the smallest possible loop area.
    • Connect split ground planes at only one point to prevent ground loops.
    • Power planes should only reference their own ground plane and should not overlap with an unrelated ground plane.
  2. Isolation: Separate digital and analog power supplies with adequate filtering and bypassing. This is critical for mixed-signal multidisciplinary boards.
  3. Decoupling Strategy:
    • Place high-quality X7R decoupling capacitors as close to device power pins as possible.
    • Use multiple capacitors (e.g., 0.1 μF, 0.01 μF, and 1 μF) in parallel to offer low impedance over a broad frequency range. Place the smallest-value capacitors closest to the pin.
    • Connect the capacitor pad directly to a via to the ground plane, using two or three vias to minimize parasitic inductance.
    • Keep traces from decoupling caps to ground short and wide.

Image of poor and good placement and routing of bypass capacitors