Skip to main content

PowerRiser for Lenovo Tiny5

The PowerRiser is an open-source, custom-engineered replacement riser card for the Lenovo Tiny5 Ultra Small Form Factor (USFF) platform. By exploiting the internal architecture of the host motherboard, it multiplexes connectivity to expose both an open-ended PCIe x8 structural link and an extra integrated M.2 NVMe slot simultaneously, matching the operational logic of stock Lenovo FRUs while expanding overall system capacity.

Buy preassembled boards:

Best for European locations (EUR currency):

Lectronz Badge

Best for International locations (USD currency):

I sell on Tindie

1. Core Hardware Specifications​

  • PCIe Interface: Physical x8 structural connector with an open-ended socket design. This permits the physical installation of full-sized x16 cards (such as standard low-profile GPUs) running at native electrical x8 speeds.
  • Secondary Storage: 1x Right-Angle M-Key M.2 Slot.
    • Supported Protocols: PCIe NVMe Gen3/Gen4 only (SATA-based M.2 drives are explicitly unsupported).
    • Mechanical Fit: Designed to accommodate standard 2230 and 2242 form-factor storage modules.
  • FRU Compatibility Emulation: Fully compatible drop-in functional alternative for Lenovo field replaceable units: 01AJ940, 01AJ902, and 01AJ929.

2. Platform Compatibility Matrix​

This custom riser card is engineered strictly for the 8th/9th Generation Intel-based Lenovo Tiny5 motherboard line.

System ModelStructural Support Profile
ThinkCentre M720qFully Supported (Plug and Play, No bifurcation required)
ThinkCentre M920qFully Supported (Plug and Play, No bifurcation required)
ThinkCentre M920xFully Supported
ThinkStation P330 TinyFully Supported
ThinkCentre M910x / P320 TinyUnsupported: Physically fits the motherboard slot but uses an incompatible pinout structure.

3. The Architecture: How It Works​

The Tiny5 motherboard routes two completely separate, independent PCIe links directly to its proprietary high-density slot wrapper:

  1. CPU Lanes: A native x8 link routed straight from the processor (historically allocated for optional discrete OEM graphics units).
  2. PCH Lanes: A secondary x4 link routed via the Platform Controller Hub (historically allocated for thunderbolt additions or quad-port network interface adapters).

The PowerRiser captures both independent tracks simultaneously without requiring manual lane bifurcation modifications or motherboard soldering. It cleanly branches the independent x8 lanes directly to the primary open-ended expansion slot while routing the completely distinct PCH x4 lane group straight into the integrated vertical M.2 storage key.

4. Mechanical & Installation Prerequisites​

:::warning Mechanical Clearance Rule To ensure optimal mechanical alignment inside the 1-Liter tiny server chassis, you must remove the metal bracket at the front of the node that holds the internal stock Bluetooth antenna module. :::

Installation Sequence​

  1. Ensure the system node is entirely powered down and the external power adapter line is decoupled.
  2. Remove the top casing sheet and dismount any existing stock riser framing or internal 2.5" SATA drive bays.
  3. Unclip and unscrew the front chassis internal structural plate holding the Bluetooth antenna frame.
  4. Align the PowerRiser card pins carefully into the high-density proprietary socket path on the motherboard and press down uniformly.
  5. Secure the riser card using the primary ground point chassis screw.
  6. Install your chosen low-profile network interface controller or computing card into the x8 open slot, and lock your 2230/2242 storage drive firmly into the vertical M-key connector.

5. Pinout Reference Matrix (Primary Bus Traces)​

The high-density proprietary header breaks out the differential Tx/Rx transmission lines from both the CPU and PCH complexes as follows:

       [ Motherboard Proprietary High-Density Slot ]
  =======================================================
   Pins 01-48: Primary Power Rails (+12V, +3.3V, GND)
   Pins 49-82: CPU Lanes (Differential Pair Lanes 0 to 7) ──> Exposed via Open-Ended x8 Slot
   Pins 83-96: PCH Lanes (Differential Pair Lanes 0 to 3) ──> Exposed via Vertical M.2 Slot
  =======================================================
Lane Assignment GroupSource DomainPin Target Allocation
PCIe Lane 0 - 7 (Tx/Rx)Intel Core CPURouted to Open-Ended Edge x8 Connector
PCIe Lane 8 - 11 (Tx/Rx)Intel PCHRouted to Right-Angle M.2 M-Key Base
Sideband Signals (CLKREQ#)System ControllerIsolated per slot node to ensure independent power state sleep modes

6. Source & Open Hardware Documentation​

This riser is an entirely open-source hardware project developed by NandFarm. If you wish to build your own, modify the traces, or review the impedance calculations, all source materials are publicly available.

  • GitHub Repository: nandfarm/PowerRiser
  • Manufacturing Assets: Schematics, BOM (Bill of Materials), and Gerber files are hosted in the repository.
  • Pre-assembled Boards: Fully assembled and tested production units can be purchased directly through the links above.